18.2.4 Initializing the LCDIF
The following initialization steps are common to all LCDIF modes of operation before entering any particular
mode.
Initialization Steps:
1. To select the pins and their directions for interfacing to the LCD panel, set the appropriate bits in
the HW_PINCTRL_MUXSELx registers in the PINCTRL block.
2. Start the PIXCLK and set the appropriate frequency by programming the registers in CLKCTRL.
3. Bring the LCDIF out of soft reset and clock gate.
4. Reset the LCD controller by setting LCDIF_CTRL1_RESET bit appropriately, being careful to
observe the reset requirements of the controller.
Select the bus interface mechanism with the LCDIF_MASTER bit in HW_LCDIF_CTRL register. If bus
master mode is enabled (LCDIF_MASTER=1), set the HW_LCDIF_CUR_BUF and
HW_LCDIF_NEXT_BUF registers by following the description in Section 18.2.1, “Bus Interface Mechanisms.
5. Set the INPUT_DATA_SWIZZLE according to the endianness of the LCD controller. Also set the
DATA_SHIFT_DIR and SHIFT_NUM_BITS if it is required to shift the data left or right before it
is output.
6. Set the WORD_LENGTH field appropriately, indicating the resolution of the pixels in the frame
buffer: 0 = 16-bit pixel, 1 = 8-bit pixel, 2 = 18-bit pixel, 3 = 24-bit pixel. Also select the correct
16/18/24 bit data format with the corresponding fields in HW_LCDIF_CTRL register.
7. Set the BYTE_PACKING_FORMAT field in HW_LCDIF_CTRL1 according to the input frame.
8. Set the LCD_DATABUS_WIDTH appropriately: 0 = 16-bit output, 1 = 8-bit output, 2 = 18-bit
output, 3 = 24-bit output.
9. Enable the necessary IRQs.

18.2.5.1 Code Example to initialize LCDIF in System mode
// Note: Common initialization steps in Section 18.2.4, “Initializing the LCDIF,” must also be
// executed along with the following code
BF_CS1(LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that the idle
state for LCD_RS signal is high, regardless of the programming of the DATA_SELECT register.
BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE);
BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in system mode
BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 1);//Only if LCD controller implements a busy line
BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2); //Values based on
PIXCLK frequency and timing requirements of controller. Note that these register must be non-zero
for correct operation.
BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240); //For a 320 RGB x 240 display
BF_CS1 (LCDIF_CTRL, RUN, 1);

Mem: 12524K used, 48748K free, 0K shrd, 0K buff, 7864K cached
CPU: 0% usr 0% sys 0% nic 98% idle 0% io 0% irq 0% sirq
Load average: 0.00 0.01 0.00 1/28 422
PID PPID USER STAT VSZ %MEM %CPU COMMAND
408 399 root R 2260 4% 0% top
421 398 root S 2704 4% 0% mc
399 1 root S 2260 4% 0% -sh
398 1 root S 2260 4% 0% -sh
1 0 root S 2180 4% 0% init
401 1 root S 2180 4% 0% /sbin/klogd -n
400 1 root S 2180 4% 0% /sbin/syslogd -n -m 0
402 1 root S 2180 4% 0% /usr/bin/tail -f /var/log/messages
422 421 root S 1596 3% 0% cons.saver /dev/tty1
5 2 root SW< 0 0% 0% [khelper]
171 2 root SW< 0 0% 0% [khubd]
337 2 root SW< 0 0% 0% [stmp3xxx_ssp.1]
2 0 root SW< 0 0% 0% [kthreadd]
3 2 root SW< 0 0% 0% [ksoftirqd/0]
4 2 root SW< 0 0% 0% [events/0]
8 2 root SW< 0 0% 0% [async/mgr]
162 2 root SW< 0 0% 0% [kblockd/0]
176 2 root SW< 0 0% 0% [kmmcd]
206 2 root SW 0 0% 0% [pdflush]
207 2 root SW 0 0% 0% [pdflush]