static struct mxs_platform_fb_entry fb_entry = {
.name = "lms430",
.x_res = 480,
.y_res = 640,
.bpp = 32,
.cycle_time_ns = 40,
.lcd_type = MXS_LCD_PANEL_DOTCLK,
.init_panel = init_panel,
.release_panel = release_panel,
.blank_panel = blank_panel,
.run_panel = mxs_lcdif_run,
.stop_panel = mxs_lcdif_stop,
.pan_display = mxs_lcdif_pan_display,
.bl_data = &bl_data,
};

red = CNVT_TOHW(red, 8);
green = CNVT_TOHW(green, 8);
blue = CNVT_TOHW(blue, 8);
transp = CNVT_TOHW(transp, 8);

#define DOTCLK_H_ACTIVE 640
#define DOTCLK_H_PULSE_WIDTH 96
#define DOTCLK_HF_PORCH 16
#define DOTCLK_HB_PORCH 12
#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH))
#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)

#define DOTCLK_V_ACTIVE 480
#define DOTCLK_V_PULSE_WIDTH 2
#define DOTCLK_VF_PORCH 10
#define DOTCLK_VB_PORCH 33
#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)

__raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) |/* 24 bit */
BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */
BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1),/* 8 bit */
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);

static struct mxs_platform_fb_entry fb_entry = {
.name = "lms430",
.x_res = 480,
.y_res = 640,
.bpp = 32,
.cycle_time_ns = 13,
.lcd_type = MXS_LCD_PANEL_DOTCLK,
.init_panel = init_panel,
.release_panel = release_panel,
.blank_panel = blank_panel,
.run_panel = mxs_lcdif_run,
.stop_panel = mxs_lcdif_stop,
.pan_display = mxs_lcdif_pan_display,
.bl_data = &bl_data,
};

#define DOTCLK_H_ACTIVE (640*3)
#define DOTCLK_H_PULSE_WIDTH (96*3)
#define DOTCLK_HF_PORCH (16*3)
#define DOTCLK_HB_PORCH (12*3)
#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH))
#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)

#define DOTCLK_V_ACTIVE 480
#define DOTCLK_V_PULSE_WIDTH 2
#define DOTCLK_VF_PORCH (10/3)
#define DOTCLK_VB_PORCH (33/3)
#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)

__raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(1) |/* 8 bit */
BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */
BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1),/* 8 bit */
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);

static struct mxs_platform_fb_entry fb_entry = {
.name = "lms430",
.x_res = 480,
.y_res = 640,
.bpp = 32,
.cycle_time_ns = 10,
.lcd_type = MXS_LCD_PANEL_DOTCLK,
.init_panel = init_panel,
.release_panel = release_panel,
.blank_panel = blank_panel,
.run_panel = mxs_lcdif_run,
.stop_panel = mxs_lcdif_stop,
.pan_display = mxs_lcdif_pan_display,
.bl_data = &bl_data,
};

#define DOTCLK_H_ACTIVE (640*4)
#define DOTCLK_H_PULSE_WIDTH (96*4)
#define DOTCLK_HF_PORCH (16*4)
#define DOTCLK_HB_PORCH (12*4)
#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH))
#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)

#define DOTCLK_V_ACTIVE 480
#define DOTCLK_V_PULSE_WIDTH 2
#define DOTCLK_VF_PORCH (10/4) // ???
#define DOTCLK_VB_PORCH (33/4) // ???
#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)

__raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(1) |/* 8 bit */
BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */
BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1),/* 8 bit */
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);

__raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(1) |/* 8 bit */
BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(1) |/* BIG_ENDIAN_SWAP = 0x1 */
BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1),/* 8 bit */
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);

#define DOTCLK_H_ACTIVE 640*4
#define DOTCLK_H_PULSE_WIDTH 96*4
#define DOTCLK_HF_PORCH 16*4
#define DOTCLK_HB_PORCH 12*4
#define DOTCLK_H_WAIT_CNT (DOTCLK_H_PULSE_WIDTH + (3 * DOTCLK_HB_PORCH))
#define DOTCLK_H_PERIOD (DOTCLK_H_WAIT_CNT + DOTCLK_HF_PORCH + DOTCLK_H_ACTIVE)

#define DOTCLK_V_ACTIVE 480
#define DOTCLK_V_PULSE_WIDTH 2
#define DOTCLK_VF_PORCH 10/4 // Без деления - не работает
#define DOTCLK_VB_PORCH 33/4
#define DOTCLK_V_WAIT_CNT (DOTCLK_V_PULSE_WIDTH + DOTCLK_VB_PORCH)
#define DOTCLK_V_PERIOD (DOTCLK_VF_PORCH + DOTCLK_V_ACTIVE + DOTCLK_V_WAIT_CNT)

static struct mxs_platform_fb_entry fb_entry = {
.name = "lms430",
.x_res = 480,
.y_res = 640,
.bpp = 32,
.cycle_time_ns = 10,
.lcd_type = MXS_LCD_PANEL_DOTCLK,
.init_panel = init_panel,
.release_panel = release_panel,
.blank_panel = blank_panel,
.run_panel = mxs_lcdif_run,
.stop_panel = mxs_lcdif_stop,
.pan_display = mxs_lcdif_pan_display,
.bl_data = &bl_data,
};

__raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF) |
BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);

__raw_writel(BM_LCDIF_CTRL_WORD_LENGTH |
BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE |
BM_LCDIF_CTRL_LCD_DATABUS_WIDTH,
REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
__raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(1) |/* 24 bit */
BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */
BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1),/* 8 bit */
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);

library ieee;
use ieee.std_logic_1164.all;

entity VGA_ALTERA is
port
(
RST_IN : in std_logic;
CLK_DOTCLK_IN : in std_logic;
HSYNC_IN : in std_logic;
VSYNC_IN : in std_logic;
ENABLE_IN : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);

R_COLOR_OUT : out std_logic_vector (7 downto 0) := X"00";
G_COLOR_OUT : out std_logic_vector (7 downto 0) := X"00";
B_COLOR_OUT : out std_logic_vector (7 downto 0) := X"00";
SYNC_OUT : out std_logic := '1';
BLANK_OUT : out std_logic := '1';
PSAVE_OUT : out std_logic := '1';
CLOCK_OUT : out std_logic := '1'

);

end entity VGA_ALTERA;

architecture VGA_ALTERA_ARCH of VGA_ALTERA is

signal green_color_reg_s, blue_color_reg_s : std_logic_vector (7 downto 0) := X"00";
signal clock_out_s, hsynk_del1, hsynk_del2 : std_logic := '0';
signal three_color_cnt_s : integer range 0 to 3 := 0;

begin


process ( CLK_DOTCLK_IN, RST_IN )
begin
if rising_edge (CLK_DOTCLK_IN) then
if (RST_IN = '0') then
R_COLOR_OUT <= X"00";
G_COLOR_OUT <= X"00";
B_COLOR_OUT <= X"00";
green_color_reg_s <= X"00";
blue_color_reg_s <= X"00";
SYNC_OUT <= '1';
BLANK_OUT <= '1';
PSAVE_OUT <= '1';
else
SYNC_OUT <= HSYNC_IN;
BLANK_OUT <= VSYNC_IN;
PSAVE_OUT <= RST_IN;

if (ENABLE_IN = '1') then
case (three_color_cnt_s) is
when 0 =>
blue_color_reg_s <= DATA_IN;
when 1 =>
green_color_reg_s <= DATA_IN;
CLOCK_OUT <= '0';
when 2 =>
R_COLOR_OUT <= DATA_IN;
G_COLOR_OUT <= green_color_reg_s;
B_COLOR_OUT <= blue_color_reg_s;
when 3 =>
CLOCK_OUT <= '1';
end case;

if (three_color_cnt_s = 3) then
three_color_cnt_s <= 0;
else
three_color_cnt_s <= three_color_cnt_s + 1;
end if;
else
end if;
end if;
end if;
end process;
end architecture VGA_ALTERA_ARCH;

static int blank_panel(int blank)
{
int ret = 0, count;

switch (blank) {
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
for (count = 10000; count; count--) {
if (__raw_readl(REGS_LCDIF_BASE + HW_LCDIF_STAT) &
BM_LCDIF_STAT_TXFIFO_EMPTY)
break;
udelay(1);
}
break;

case FB_BLANK_UNBLANK:
__raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
break;

default:
ret = -EINVAL;
}
return ret;
}