MX53_PAD_GPIO_9__PWM1_PWMO,

static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
.pwm_id = 0,
.max_brightness = 255,
.dft_brightness = 128,
.pwm_period_ns = 50000,
};

mxc_register_device(&mxc_pwm1_device, NULL);
mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data);

#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <unistd.h>

//-------------------------------------------------------------

#define IMX_CLK_REG 0x53fd4000 /* CLK registers */
#define IMX_IOMUXC 0x53fa8000 /* IOMUXC registers */
#define IMX_PWM1 0x53fb4000 /* PWM 1 registers */

#define PWM_PWMCR 0x00 /* Control register */
#define PWM_PWMSR 0x04 /* Status register */
#define PWM_PWMIR 0x08 /* Interrupt register */
#define PWM_PWMSAR 0x0c /* Sample register */
#define PWM_PWMPR 0x10 /* Period register */
#define PWM_PWMCNR 0x14 /* Counter register */

//-------------------------------------------------------------

#define MAP_BASE_PWM1 (IMX_PWM1)
#define MAP_BASE_IOMUXC (IMX_IOMUXC)
#define MAP_BASE_CLK (IMX_CLK_REG)
#define MAP_SIZE 4096Ul
#define MAP_MASK (MAP_SIZE - 1)

#define IOMUXC_SW_MUX_CTL_PAD_GPIO9 0x31C

#define CCM_CCGR2 0x70

void *mapped_base_clk;
void *mapped_base_pwm1;
void *mapped_base_iomuxc;

//-----------------------------------------------------------------------

int main(void)
{
unsigned int i;

int fd;

// try open /dev/mem ===============================================

if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1)
{
printf("Cannot open /dev/mem.\n");
exit(EXIT_FAILURE);
}

printf("/dev/mem opened.\n");

// try mapped memory CLK =============================================

mapped_base_clk = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MAP_BASE_CLK & ~MAP_MASK);
if (mapped_base_clk == (void *) -1)
{
printf("Memory mapping error.\n");
exit(EXIT_FAILURE);
}

printf("CCM memory block mapped at address %p.\n", mapped_base_clk);
mapped_base_clk+=(MAP_BASE_CLK & MAP_MASK);
printf("Target address mapped 0x%08x-->0x%08x\n",(int) MAP_BASE_CLK,(int)mapped_base_clk);

//==================================================================

printf("Initing CLK Module\n");

*(int*)(mapped_base_clk+CCM_CCGR2) |= 0xC00; // ipg_clk

// try mapped memory IOMUXC =============================================

/* mapped_base_iomuxc = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MAP_BASE_IOMUXC & ~MAP_MASK);
if (mapped_base_iomuxc == (void *) -1)
{
printf("Memory mapping error.\n");
exit(EXIT_FAILURE);
}

printf("IOMUXC memory block mapped at address %p.\n", mapped_base_iomuxc);
mapped_base_iomuxc+=(MAP_BASE_IOMUXC & MAP_MASK);
printf("Target address mapped 0x%08x-->0x%08x\n",(int) MAP_BASE_IOMUXC,(int)mapped_base_iomuxc);
*/
//==================================================================
/*
printf("Initing IOMUX Module\n");

*(int*)(mapped_base_iomuxc+IOMUXC_SW_MUX_CTL_PAD_GPIO9) = 4; // GPIO9 -> PWM
*/
// try mapped memory PWM1 =============================================

mapped_base_pwm1 = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, MAP_BASE_PWM1 & ~MAP_MASK);
if (mapped_base_pwm1 == (void *) -1)
{
printf("Memory mapping error.\n");
exit(EXIT_FAILURE);
}

printf("PWM1 memory block mapped at address %p.\n", mapped_base_pwm1);
mapped_base_pwm1+=(MAP_BASE_PWM1 & MAP_MASK);
printf("Target address mapped 0x%08x-->0x%08x\n",(int) MAP_BASE_PWM1,(int)mapped_base_pwm1);


//==================================================================

printf("Initing PWM 1 Module\n");

*(int*)(mapped_base_pwm1+PWM_PWMCR) = 0; // Disable PWM
*(int*)(mapped_base_pwm1+PWM_PWMCR) = 0x3C10000;
*(int*)(mapped_base_pwm1+PWM_PWMSR) = 0;
*(int*)(mapped_base_pwm1+PWM_PWMIR) = 0;
*(int*)(mapped_base_pwm1+PWM_PWMSAR) = 300;
*(int*)(mapped_base_pwm1+PWM_PWMPR) = 600;

*(int*)(mapped_base_pwm1+PWM_PWMCR) |= 1; // Enable PWM

printf("PWM 1 Module - Enabled\n");

while(1)
{
// printf("Counter status 0x%08x\n",(*(int*)(mapped_base_pwm1+PWM_PWMCNR)));
// for (i=0;i<10000;i++);
}

close(fd);
printf("Bye!\n");
return 0;
}