pinctrl@fffff200 {
fpga0 {
pinctrl_board_fpga0: fpga0-board {
atmel,pins =
<AT91_PIOC 10 AT91_PERIPH_GPIO AT91_PINCTRL_NONE /* PC10 for CCLK */
AT91_PIOC 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE /* PC11 for DIN */
AT91_PIOC 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC29 for DONE */
AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC30 for PROG */
AT91_PIOE 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE0 for PCK0 */
>;
};
};
};
...
fpga@0 {
compatible = "sk,fpga";
reg = <0 0x0 0x500>;

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_board_fpga0>;

clocks = <&pck0>;
clock-names = "fpgaclk";
assigned-clocks = <&pck0>;
assigned-clock-rates = <50000000>;
};

struct clk *fclk;

fclk=devm_clk_get(&platdev->dev, "fpgaclk");
if(IS_ERR(fclk)) {
dev_err(&platdev->dev, "Failed to get fpga clock\n");
return -EINVAL;
}
if(result=clk_prepare_enable(fclk))
{
dev_err("%s: error preparing fpga clock, returned %d", __func__, result);
return result;
}