U-Boot> loady
## Ready for binary (ymodem) download to 0x21000000 at 115200 bps...
CC

U-Boot> go 0x21000000
## Starting application at 0x21000000 ...

#ifndef BOARD_H
#define BOARD_H

//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------

#if defined(at91sam9xe128)
#include "at91sam9xe128/chip.h"
#include "at91sam9xe128/AT91SAM9XE128.h"
#elif defined(at91sam9xe256)
#include "at91sam9xe256/chip.h"
#include "at91sam9xe256/AT91SAM9XE256.h"
#elif defined(at91sam9xe512)
#include "at91sam9xe512/chip.h"
#include "at91sam9xe512/AT91SAM9XE512.h"
#else
#error Board does not support the specified chip.
#endif

//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - Board Description"
/// This page lists several definition related to the board description.
///
/// !Definitions
/// - BOARD_NAME

/// Name of the board.
#define BOARD_NAME "AT91SAM9XE-EK"
/// Board definition.
#define at91sam9xeek
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
/// \page "SAM9XE-EK - Operating frequencies"
/// This page lists several definition related to the board operating frequency
/// (when using the initialization done by board_lowlevel.c).
///
/// !Definitions
/// - BOARD_MAINOSC
/// - BOARD_MCK

/// Frequency of the board main oscillator.
#define BOARD_MAINOSC 18432000

/// Master clock frequency (when using board_lowlevel.c).
#define BOARD_MCK ((18432000 * 97 / 9) / 2)
//------------------------------------------------------------------------------

/// Main oscillator startup time (in number of slow clock ticks).
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))

/// PLLA frequency range.
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)
/// PLLA startup time (in number of slow clock ticks).
#define BOARD_PLLACOUNT (63 << 8)
/// PLLA MUL value.
#define BOARD_MULA (AT91C_CKGR_MULA & (49 << 16))
/// PLLA DIV value.
#define BOARD_DIVA (AT91C_CKGR_DIVA & 3)

/// PLLB frequency range
#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_0
/// PLLB startup time (in number of slow clock ticks).
#define BOARD_PLLBCOUNT BOARD_PLLACOUNT
/// PLLB MUL value.
#define BOARD_MULB (175 << 16)
/// PLLB DIV value.
#define BOARD_DIVB 15

/// USB PLL divisor value to obtain a 48MHz clock.
#define BOARD_USBDIV AT91C_CKGR_USBDIV_2
/// Master clock prescaler value.
#define BOARD_PRESCALER AT91C_PMC_MDIV_2

/// Frequency of the board main oscillator.
#define BOARD_MAINOSC 12000000

/// Master clock frequency (when using board_lowlevel.c).
#define BOARD_MCK ((12000000 * 50 / 3) / 2)