case DDR_SAMSUNG_M470T6554EZ3_CE6:

// Step 1: Program the memory device type
WRITE(pDdrc, HDDRSDRC2_MDR, ddrc_dbw |
AT91C_DDRC2_MD_DDR2_SDRAM); // DDR2

// Step 2:
// 1. Program the features of DDR2-SDRAM device into the Configuration Register.
// 2. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T0PR.
// 3. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T1PR.
// 4. Program the features of DDR2-SDRAM device into the Timing Register HDDRSDRC2_T2PR.
WRITE(pDdrc, HDDRSDRC2_CR, AT91C_DDRC2_NC_DDR10_SDR9 | // 10 column bits (1K)
AT91C_DDRC2_NR_13 | // 13 row bits (8K)
AT91C_DDRC2_CAS_3 | // CAS Latency 3
AT91C_DDRC2_DLL_RESET_DISABLED); // DLL not reset

// assume timings for 7.5ns min clock period
WRITE(pDdrc, HDDRSDRC2_T0PR, AT91C_DDRC2_TRAS_6 | // 6 * 7.5 = 45 ns
AT91C_DDRC2_TRCD_2 | // 2 * 7.5 = 15 ns
AT91C_DDRC2_TWR_2 | // 2 * 7.5 = 15 ns
AT91C_DDRC2_TRC_8 | // 8 * 7.5 = 60 ns
AT91C_DDRC2_TRP_2 | // 2 * 7.5 = 15 ns
AT91C_DDRC2_TRRD_2 | // 1 * 7.5 = 7.5 ns
AT91C_DDRC2_TWTR_1 | // 1 clock cycle
AT91C_DDRC2_TMRD_2); // 2 clock cycles


WRITE(pDdrc, HDDRSDRC2_T1PR, AT91C_DDRC2_TXP_2 | // 2 * 7.5 = 15 ns
200 << 16 | // 200 clock cycles, TXSRD: Exit self refresh delay to Read command
16 << 8 | // 16 * 7.5 = 120 ns TXSNR: Exit self refresh delay to non read command
AT91C_DDRC2_TRFC_14 << 0); // 14 * 7.5 = 105 ns (must be 105 ns for 512M DDR)


WRITE(pDdrc, HDDRSDRC2_T2PR, AT91C_DDRC2_TRTP_1 | // 1 * 7.5 = 7.5 ns
AT91C_DDRC2_TRPA_0 |
AT91C_DDRC2_TXARDS_7 | // 7 clock cycles
AT91C_DDRC2_TXARD_2); // 2 clock cycles

// Step 3: An NOP command is issued to the DDR2-SDRAM to enable clock.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*pDdr = 0;

// Initialization Step 3 (must wait 200 us) (6 core cycles per iteration, core is at 396MHz: min 13200 loops)
for (i = 0; i < 13300; i++) {
asm(" nop");
}
// Step 4: An NOP command is issued to the DDR2-SDRAM
// NOP command -> allow to enable cke
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*pDdr = 0;

// wait 400 ns min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*pDdr = 0;

// wait 400 ns min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 6: An Extended Mode Register set (EMRS2) cycle is issued to chose between commercialor high temperature operations.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x2000000)) = 0; // BA[1] is set to 1 and BA[0] are set to 0.

// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 7: An Extended Mode Register set (EMRS3) cycle is issued to set all registers to 0.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x3000000)) = 0; //BA[1] is set to 1 and BA[0] are set to 1.

// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 8: An Extended Mode Register set (EMRS1) cycle is issued to enable DLL.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr)) = 0; //BA[1] and BA[0] are set to 0.

// wait 200 cycles min
for (i = 0; i < 10000; i++) {
asm(" nop");
}

// Step 9: Program DLL field into the Configuration Register.
cr = READ(pDdrc, HDDRSDRC2_CR);
WRITE(pDdrc, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);

// Step 10: A Mode Register set (MRS) cycle is issued to reset DLL.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*(pDdr) = 0;

// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(pDdr) = 0;

// wait 400 ns min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(pDdr) = 0;

// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}
// Set 2nd CBR
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(pDdr) = 0;

// wait 10 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
cr = READ(pDdrc, HDDRSDRC2_CR);
WRITE(pDdrc, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));

// Step 14: A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*(pDdr) = 0; //BA[1:0] are set to 0.

// Step 15: Program OCD field into the Configuration Register to high (OCD calibration default).
cr = READ(pDdrc, HDDRSDRC2_CR);
WRITE(pDdrc, HDDRSDRC2_CR, cr | AT91C_DDRC2_OCD_DEFAULT);

// Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x1000000)) = 0; //BA[1] is set to 0 and BA[0] is set to 1

// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 17: Program OCD field into the Configuration Register to low (OCD calibration mode exit).
cr = READ(pDdrc, HDDRSDRC2_CR);
WRITE(pDdrc, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_OCD_EXIT));

// Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)((unsigned char *)pDdr + 0x3000000)) = 0; //BA[1] is set to 1and BA[0] is set to 1.

// wait 2 cycles min
for (i = 0; i < 100; i++) {
asm(" nop");
}

// Step 19,20: A mode Normal command is provided. Program the Normal mode into Mode Register.
WRITE(pDdrc, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(pDdr) = 0;

// Step 21: Write the refresh rate into the count field in the Refresh Timer register. The DDR2-SDRAM device requires a
// refresh every 15.625 s or 7.81 s. With a 100MHz frequency, the refresh timer count register must to be set with
// (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100MHz) = 781 i.e. 0x030d.

// Set Refresh timer
WRITE(pDdrc, HDDRSDRC2_RTR, 0x00000411);

// OK now we are ready to work on the DDRSDR

// wait for end of calibration
for (i = 0; i < 500; i++) {
asm(" nop");
}

break;